1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor device the failure of which can be redressed based on a test result.
2. Description of the Related Art
In recent years, a semiconductor memory device has become smaller and grown in capacity, and needs to be subjected to a screening test several times. In the conduct of the screening test, a semiconductor memory device has conventionally been redressed through replacement of a separately-arising defective memory cell with a spare memory cell by fuse cutting (such a redress technique is hereinafter referred to as replacement redress). To carry out such replacement redress several times, however, addition and review of a test circuit and addition of a dedicated signal line for controlling replacement redress are required. Consequently, a chip size becomes larger, which results in a cost increase. What is needed to avoid this is a several-time replacement redress circuit not requiring external control and operations. A conventional semiconductor memory device having a replacement redress circuit is described in Japanese Patent Application Publication No. 2001-23393, for example.
FIG. 6 is a block diagram for explaining a configuration of a conventional replacement control circuit 24. The replacement control circuit 24 includes a complementary address generation circuit 42, a fuse selection circuit 44, a replacement address setting circuit 46, and a decoder deactivation circuit 48. The complementary address generation circuit 42 receives a fuse selection address signal BSEL provided to select a fuse for storing an address to be replaced, outputs the signal as it is upon a first conduct of replacement, and outputs a complementary address upon a second conduct of replacement. The fuse selection circuit 44 outputs a fuse selection signal BSIG in response to the output from the complementary address generation circuit 42 and an address strobe signal /AS. The replacement address setting circuit 46 outputs a spare selection signal SPSEL in response to an address signal AD externally inputted and the fuse selection signal BSIG. The decoder deactivation circuit 48 deactivates a main address decoder 50 when the spare selection signal SPSEL is activated. When the spare selection signal SPSEL is activated, a spare address decoder 54 decodes the spare selection signal SPSEL and activates a corresponding spare memory cell 56.
FIG. 7 is a circuit diagram showing a configuration of the complementary address generation circuit 42 in FIG. 6. The complementary address generation circuit 42 has a circuit 42#0 and a circuit 42#1. The circuit 42#0 outputs a signal BSEL0a upon receipt of a fuse selection address signal BSEL0, and the circuit 42#1 outputs a signal BSEL1a upon receipt of a fuse selection address signal BSEL1. The circuit 42#0 has: an n-channel MOS transistor 68 that is activated upon receipt of an identification signal SID at a gate thereof when first redundancy replacement is complete and conveys a high voltage BV to a node N1; a resistor 67 that is connected between a power node to which a power supply potential Vcc is provided and the node N1; and an antifuse 66 that is connected between the node N1 and a ground node. The antifuse is a type of electrical fuse and has a property of becoming conductive between electrodes by being blown. In other words, the antifuse 66 becomes conductive when the high voltage BV is applied to the node N1, which causes the node N1 to have the approximately same potential as the ground node. Hence, the node N1 is at the H level before a first fuse blowing, but is at the L level after the first fuse blowing. To be more specific, the node N1 is at the L level when a second fuse blowing is needed as a result of a subsequent test performed after undergoing operational states such as normal read/write operations, other test operations, standby mode or shut-down after leaving replacement redress mode. The circuit 42#0 further has: an n-channel MOS transistor 62 being connected between nodes N2 and N3 and having a gate connected to the node N1; an inverter 70 that receives and reverses the fuse selection address signal BSEL0 provided to the node N2 and outputs the reversed fuse selection address signal BSEL0 to a node N4; and a p-channel MOS transistor 64 being connected between the nodes N4 and N3 and having a gate connected to the node N1.
The node N3 outputs the signal BSEL0a being the output of the complementary address generation circuit 42. FIG. 7 shows only the fuse selection address signal BSEL0 in detail; however, in the similar way, the similar circuit 42#1 is provided with the fuse selection address signal BSEL1 and outputs the signal BSEL1a correspondingly. Since the node N1 is at the H level when the first fuse blowing is to be performed, the n-channel MOS transistor 62 is conductive, and therefore the fuse selection address signal BSEL0 provided to the node N2 is conveyed to the node N3 as it is. On the other hand, since the node N1 is at the L level when the second fuse blowing is to be performed as described before, the n-channel MOS transistor 62 is nonconductive, and therefore the p-channel MOS transistor 64 connected between the nodes N4 and N3 becomes conductive instead. Consequently, the fuse selection address signal BSEL0 is reversed by the inverter 70.
FIG. 8 is a circuit diagram showing a configuration of the fuse selection circuit 44 in FIG. 6. The fuse selection circuit 44 has: a fuse selection decoder 82 that receives and decodes the signals BSEL0a and BSEL1a, which are the output signals of the complementary address generation circuit 42; an inverter 84 that receives and reverses the strobe signal /AS of a row or column address; a NOR circuit 86 that outputs a fuse selection signal BSIG0 upon receipt of an output signal BSIG0a of the fuse selection decoder 82 and the output signal of the inverter 84; a NOR circuit 88 that outputs a fuse selection signal BSIG1 upon receipt of an output signal BSIG1a of the fuse selection decoder 82 and the output signal of the inverter 84; a NOR circuit 90 that outputs a fuse selection signal BSIG2 upon receipt of an output signal BSIG2a of the fuse selection decoder 82 and the output signal of the inverter 84; and a NOR circuit 92 that outputs a fuse selection signal BSIG3 upon receipt of an output signal BSIG3a of the fuse selection decoder 82 and the output signal of the inverter 84. The fuse selection decoder 82 receives and decodes the signals BSEL0a and BSEL1a, and activates any one of the output signals BSIG0a to BSIG3a. The NOR circuits 86 to 92 activate all the fuse selection signals BSIG0 to BSIG3 upon activation of the strobe signal /AS when a row or column address is externally inputted. When the strobe signal /AS is deactivated, the NOR circuits 86 to 92 output, as the fuse selection signals BSIG0 to BSIG3, the signals BSIG0a to BSIG3a decoded in response to the fuse selection address signal BSEL externally provided.
As described above, the conventional technology requires a replacement information holding circuit to have a circuit which changes a selected fuse set when replacement redress is necessary. Moreover, the replacement information holding circuit also requires a special control circuit and control procedure for storing, in a nonvolatile manner, a fact that a first replacement redress process has been carried out and completed after completing replacement redress for the required number of defective word and bit lines, and the like, as the first replacement redress. Since circuits to be added in this manner are repeatedly placed for each required replacement redress, a chip size increases and the control procedure becomes more complicated.